Apart from IBM, Intel, Taiwan Semiconductor Manufacturing Co., and Samsung, which have strong R&D technical strength in the semiconductor process, The Belgium research institute IMEC have developed SGTs (Surrounding Gate Transistors) in cooperation with Singapore-based Unisantis, which enables 5-nm 6-transistor SRAM cells.
Miniaturization is the A & O in semiconductor technology. The further validity of Moore’s Law is contrary to the fact that the structures are inexorably approaching the size of individual atoms. Unisantis vertical surround-gate technology now allows a six-transistor SRAM cell to be compressed to an unbelievably small area of 0.0184 to 0.0205 μm². A cell based on such SGTs requires a 20 to 30% reduction in area compared to horizontal SGTs. In addition, there are advantages in the operating voltage and stability.
With the Vertical Surround Gates, the channel of the FET is almost perfectly controlled. A built-in SRAM cell allows an area of only 0.0205 μm² with a minimum pillar pitch of 50 nm, resulting in 24% better area utilization compared to the smallest conventional SRAM cells. The manufacturing costs should be comparable to conventional finFET-based SRAMs if the number of process steps by EUV lithography is kept low.
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